A Fast , Accurate , and Non - statistical Method for Fault Coverage

We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by signiicantly reducing the number of injected faults and faulty-event evaluations. Speciically, we dynamically reduce injection of two types of faults: (1) hyperactive faults that never get detected, and (2) faults whose effects never propagate to a ip-op or primary output. The cost of fault simulation is greatly reduced as injection of most of these two types of faults is prevented. Experiments show that our technique gives very accurate estimates with frequently greater speedups than the sampling techniques for most circuits. Most signiicantly, the proposed technique can be combined with the sampling approach to obtain speedups equivalent of small sample sizes and retain estimation accuracy of large fault samples. Fault coverage estimation techniques attempt to quickly and accurately estimate the fault coverage from a given test set. As complexity and size of VLSI circuits steadily increase, fast and reliable fault coverage estimation will become more widely used, especially for relieving the high cost of full fault simulation in large circuits. Traditionally, statistical methods have been used for fault coverage estimation; these include statistical fault analysis techniques 1, 2], fault-sampling methods 3, 4], as well as vector-sampling techniques 5]. Fault analysis techniques 1, 2] are based on detection probabilities of faults via fault-free simulation. Though fast, this technique is useful only to combinational circuits for ensuring reliable estimates, since most faults in sequential circuits frequently require propagation of several time frames before detection. Statistical vector-sampling 5] is based on a similar idea of detection probabilities, except that the total number of vectors simulated is reduced. Again, only combinational circuits will beneet from sampling vectors because sequential circuits place considerable constraints on the traversal of the state space to ensure detection of a fault. Statistical fault sampling 3, 4], unlike the previous two techniques, can be applied to both combinational and sequential circuits with good conndence of accuracy when the sample size is suuciently large. While the previous fault coverage estimation methods 1-5] attempted to reduce the execution time by statistically reducing the work involved, the approach presented in this paper is not based on statistical analysis or sampling. Instead , it avoids simulation of faults that are unlikely to be detected. Since fault simulators spend most of their time in evaluating sporadic events 6], it would be extremely ben-eecial if the sporadic events …